Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 18
Q461:
In the RTL, what does the instruction rfi (Return from Interrupt) do?
A. Disables interrupt
B. Enables exception
C. Returns from an interrupt
D. Saves instruction execution state
Correct Answer:
C
Chapter: 18
Q462:
What does pipelining improve in terms of processor performance?
A. Latency
B. Efficiency
C. Throughput
D. Memory access speed
Correct Answer:
C
Chapter: 18
Q463:
In which stage of a pipeline does memory access happen?
A. Instruction fetch
B. ALU operation
C. Memory access
D. Register write
Correct Answer:
C
Chapter: 18
Q464:
Which of the following is NOT a complication in pipelining?
A. Data dependence
B. Branch delay
C. Load delay
D. Register write stalls
Correct Answer:
D
Chapter: 18
Q465:
Pipelining affects which of the following?
A. Latency
B. Instruction execution speed
C. Instruction set
D. Throughput
Correct Answer:
D
Chapter: 18
Q466:
Which instruction in the pipeline might need to be stalled due to data dependence?
A. load r2, 34(r1)
B. add r3, r2, r1
C. sub r4, r5, r3
D. mov r1, r2
Correct Answer:
B
Chapter: 18
Q467:
What method is used to resolve branch delay in pipelining?
A. NOP instruction
B. Data forwarding
C. ALU stalls
D. Memory access stalls
Correct Answer:
A
Chapter: 18
Q468:
In which stage of the pipeline is the instruction fetched from memory?
A. Instruction decode
B. ALU operation
C. Instruction fetch
D. Register write
Correct Answer:
C
Chapter: 18
Q469:
What is the main advantage of separating instruction memory and data memory in a pipeline?
A. Decreases latency
B. Improves throughput
C. Prevents pipeline stalls
D. Allows instructions to be fetched while data is loaded
Correct Answer:
D
Chapter: 18
Q470:
Fill in the blank: Data forwarding allows the result from the ______ stage to be transferred directly to the decode stage of the next instruction.
A. Memory access
B. Instruction fetch
C. Execute
D. Register write
Correct Answer:
C
Chapter: 18
Q471:
Which of the following instructions could cause a load delay?
A. add r3, r2, r1
B. load r2, 34(r1)
C. sub r4, r5, r3
D. mov r1, r2
Correct Answer:
B
Chapter: 18
Q472:
What is the time required to process a single instruction called?
A. Latency
B. Throughput
C. Execution time
D. Pipeline stall
Correct Answer:
A
Chapter: 18
Q473:
In a non-pipelined machine, how many cycles are required to complete one instruction?
A. 1
B. 3
C. 5
D. 10
Correct Answer:
C
Chapter: 18
Q474:
What happens in the memory access stage of the pipeline?
A. Read from memory
B. Write to memory
C. Both A and B
D. Neither A nor B
Correct Answer:
C
Chapter: 19
Q475:
What are the stages of the SRC pipeline?
A. Instruction Fetch, ALU, Memory Access
B. Instruction Decode, ALU, Branches
C. Instruction Fetch, ALU, Register
D. Instruction Fetch, ALU, Memory
Correct Answer:
A
Chapter: 19
Q476:
In a pipelined SRC, which register holds the fetched instruction?
A. IR1
B. IR2
C. IR3
D. IR4
Correct Answer:
B
Chapter: 19
Q477:
What does X3 in the pipeline store during ALU instruction execution?
A. Constant from instruction
B. Operand value from memory
C. Operand value from register file
D. Operand value from PC
Correct Answer:
C
Chapter: 19
Q478:
Which register holds the result of the ALU operation?
A. X3
B. Y3
C. Z4
D. Z5
Correct Answer:
C
Chapter: 19
Q479:
In which stage does register Z5 hold the value for writing back?
A. Instruction Fetch
B. Memory Access
C. Write-back
D. ALU Operation
Correct Answer:
C
Chapter: 19
Q480:
What does Mp1 control in the pipeline?
A. ALU operations
B. Memory access
C. PC input
D. Register write-back
Correct Answer:
C