Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 20
Q501:
How does the SRC pipeline resolve data hazards?
A. Using NOP instructions
B. By stalling
C. By using data forwarding
D. Both B and C
Correct Answer:
D
Chapter: 20
Q502:
The instruction alu3&alu2&((ra3=rb2)~((ra3=rc2)&!imm2)) in RTL detects:
A. A branch hazard
B. A structural hazard
C. A data hazard
D. A memory access error
Correct Answer:
C
Chapter: 20
Q503:
Which instruction does NOT access memory in the pipeline cycle?
A. Add
B. Load
C. Store
D. Branch
Correct Answer:
A
Chapter: 20
Q504:
The result of an ALU operation is typically available at which stage?
A. Stage 1
B. Stage 2
C. Stage 3
D. Stage 4
Correct Answer:
C
Chapter: 20
Q505:
Fill in the blank: Data forwarding transfers data from stage 3 to stage ____.
A. Stage 1
B. Stage 2
C. Stage 4
D. Stage 5
Correct Answer:
B
Chapter: 21
Q506:
What is Instruction Level Parallelism?
A. Executing multiple instructions in a sequence
B. Executing multiple instructions in parallel
C. Executing one instruction per clock cycle
D. None of the above
Correct Answer:
B
Chapter: 21
Q507:
Which of the following is a feature of Superscalar Architecture?
A. Only one functional unit
B. One instruction executed at a time
C. Multiple instructions executed in parallel
D. Single pipeline
Correct Answer:
C
Chapter: 21
Q508:
In pipelining, how are instructions executed?
A. Sequentially
B. In parallel
C. Overlapped in different stages
D. In reverse order
Correct Answer:
C
Chapter: 21
Q509:
What is the purpose of the Branch Prediction Unit (BPU)?
A. To decode instructions
B. To predict branch target addresses
C. To manage data forwarding
D. To handle floating-point operations
Correct Answer:
B
Chapter: 21
Q510:
Which of the following architectures uses very long instruction words?
A. Superscalar
B. Pipelined
C. VLIW
D. RISC
Correct Answer:
C
Chapter: 21
Q511:
What is the primary goal of the Superscalar Design?
A. To simplify instruction execution
B. To increase clock speed
C. To fetch and decode multiple instructions before execution
D. To reduce hardware requirements
Correct Answer:
C
Chapter: 21
Q512:
How are instructions issued in Instruction Level Parallelism?
A. Sequentially
B. In parallel
C. In random order
D. In reverse order
Correct Answer:
B
Chapter: 21
Q513:
Which of the following is NOT a feature of pipelining?
A. Single functional unit
B. Instructions issued sequentially
C. Instructions executed in parallel
D. Minimal extra hardware required
Correct Answer:
C
Chapter: 21
Q514:
Which functional units are part of Superscalar Architecture?
A. Integer Units, Floating Point Units, Branch Prediction Units
B. ALU, Register File, Control Unit
C. Cache, RAM, ROM
D. GPU, DSP, FPU
Correct Answer:
A
Chapter: 21
Q515:
How does a VLIW processor handle instruction execution?
A. At runtime
B. Using branch prediction
C. At compile time
D. Using multiple pipelines
Correct Answer:
C
Chapter: 21
Q516:
What is the width of a typical VLIW instruction word?
A. 32 bits
B. 64 or 128 bits
C. 16 bits
D. 8 bits
Correct Answer:
B
Chapter: 21
Q517:
Superscalar processors use which technique to improve instruction-level parallelism?
A. Data forwarding
B. Pipelining
C. Speculative execution
D. All of the above
Correct Answer:
D
Chapter: 21
Q518:
Which processor is an example of a Superscalar architecture?
A. Intel P6
B. ARM Cortex-A9
C. Intel 8086
D. PowerPC 601
Correct Answer:
A
Chapter: 21
Q519:
Fill in the blank: _______ architecture uses very long instruction words to achieve instruction-level parallelism.
A. Superscalar
B. VLIW
C. Pipelined
D. RISC
Correct Answer:
B
Chapter: 21
Q520:
Fill in the blank: In a Superscalar processor, multiple _______ can execute in parallel.
A. Pipelines
B. ALUs
C. Cache lines
D. Registers
Correct Answer:
A