Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Chapter: 0
Q1:
In the binary number “10011” the weight of the most significant digit is
A. 2^4
B. 2^3
C. 2^0
D. 2^1
Correct Answer:
A
Chapter: 0
Q2:
An S-R latch can be implemented by using _________ gates
A. AND, OR
B. NAND, NOR
C. NAND, XOR
D. NOT, XOR
Correct Answer:
B
Chapter: 0
Q3:
A latch has _____ stable states
A. One
B. Two
C. Three
D. Four
Correct Answer:
B
Chapter: 0
Q4:
The ABEL symbol for “XOR” operation is
A. $
B. #
C. !
D. &
Correct Answer:
B
Chapter: 0
Q5:
Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
A. A parallel to serial converter circuit
B. A counter circuit
C. A BCD to Decimal decoder
D. A 2-to-8 bit decoder
Correct Answer:
B
Chapter: 0
Q6:
The device shown here is most likely a
A. Comparator
B. Multiplexer
C. Demultiplexer
D. Parity generator
Correct Answer:
B
Chapter: 0
Q7:
The main use of the Multiplexer is to
A. Select data from multiple sources and to route it to a single Destination
B. Select data from Single source and to route it to a multiple Destinations
C. Select data from Single source and to route to single destination
D. Select data from multiple sources and to route to multiple destinations
Correct Answer:
A
Chapter: 0
Q8:
A logic circuit with an output consists of ________.
A. two AND gates, two OR gates, two inverters
B. three AND gates, two OR gates, one inverter
C. two AND gates, one OR gate, two inverters
D. two AND gates, one OR gate
Correct Answer:
B
Chapter: 0
Q9:
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
A. 4
B. 8
C. 12
D. 16
Correct Answer:
B
Chapter: 0
Q10:
The output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol’+’ here represents OR Gate.
A. Undefined
B. One
C. Zero
D. 10 (binary)
Correct Answer:
B
Chapter: 0
Q11:
The Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code
A. 2-bit
B. 7-bit
C. 8-bit
D. 16-bit
Correct Answer:
C
Chapter: 0
Q12:
The diagram given below represents __________
A. Demorgans law
B. Associative law
C. Product of sum form
D. Sum of product form
Correct Answer:
B
Chapter: 0
Q13:
GAL can be reprogrammed because instead of fuses _______ logic is used in it
A. E2 CMOS
B. TTL
C. CMOS+
D. None of the given options
Correct Answer:
A
Chapter: 0
Q14:
If “1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:
A. 2nd
B. 4th
C. 14th
D. No output wire will be activated
Correct Answer:
D
Chapter: 0
Q15:
A particular Full Adder has
A. 3 inputs and 2 output
B. 3 inputs and 3 output
C. 2 inputs and 3 output
D. 2 inputs and 2 output
Correct Answer:
B
Chapter: 0
Q16:
C B A Sum ⊕ ⊕ = AB B A C CarryOut + ⊕ = ) ( are the Sum and CarryOut expression of
A. Half Adder
B. Full Adder
C. 3-bit parallel adder
D. MSI adder circuit
Correct Answer:
B
Chapter: 0
Q17:
The output A < B is set to 1 when the input combinations is __________
A. A=10, B=01
B. A=11, B=01
C. A=01, B=01
D. A=01, B=10
Correct Answer:
A
Chapter: 0
Q18:
The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
A. 4
B. 8
C. 12
D. 16
Correct Answer:
D
Chapter: 0
Q19:
Generally, the Power dissipation of _______ devices remains constant throughout their operation.
A. TTL
B. CMOS 3.5 series
C. CMOS 5 Series
D. Power dissipation of all circuits increases with time.
Correct Answer:
C
Chapter: 0
Q20:
The decimal “8” is represented as _________ using Gray-Code.
A. 11
B. 1100
C. 1000
D. 1010
Correct Answer:
C