Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 16
Q421:
The Boolean equation for PCout includes which steps?
A. T0 and T2
B. T3 with OP20 and OP22
C. T5 with CON
D. T1 and T4
Correct Answer:
B
Chapter: 16
Q422:
What signal is used to read the Program Counter during instruction fetch?
A. MAR
B. MBR
C. PCout
D. R2BUS
Correct Answer:
C
Chapter: 16
Q423:
Which component checks the condition in branch instructions?
A. ALU
B. CON circuitry
C. RBE signal
D. Instruction Decoder
Correct Answer:
B
Chapter: 16
Q424:
What is the minimum time required to transfer data from one register to another?
A. Clock cycle time
B. tg + tbp + tcomb + t1
C. Propagation delay
D. Time interval T0-T7
Correct Answer:
B
Chapter: 16
Q425:
Which signal is used to enable a read of the Program Counter?
A. INC4
B. LPC
C. PCout
D. MRead
Correct Answer:
C
Chapter: 16
Q426:
In the 2-bus implementation, which bus is used for reading values from components?
A. Out bus
B. In bus
C. Data bus
D. Address bus
Correct Answer:
A
Chapter: 16
Q427:
The Control Unit is represented using which type of machine?
A. Infinite-state machine
B. Finite-state machine
C. Virtual machine
D. Turing machine
Correct Answer:
B
Chapter: 16
Q428:
What function does the ALSU perform during instruction fetch?
A. Decrement-by-four
B. Shift operation
C. Increment-by-four
D. Data masking
Correct Answer:
C
Chapter: 16
Q429:
The FALCON-A processor has how many bits for the opcode?
A. 16 bits
B. 5 bits
C. 8 bits
D. 32 bits
Correct Answer:
B
Chapter: 16
Q430:
The maximum clock frequency in a control unit is limited by what factor?
A. Propagation delay of gates
B. Bus width
C. Memory read speed
D. Instruction fetch time
Correct Answer:
A
Chapter: 16
Q431:
Which step is responsible for loading the Memory Address Register (MAR) during instruction fetch?
A. T0
B. T1
C. T2
D. T3
Correct Answer:
A
Chapter: 17
Q432:
What is the purpose of a reset operation in a processor?
A. To execute the next instruction
B. To modify memory contents
C. To reload the PC to a predefined value
D. To interrupt the current process
Correct Answer:
C
Chapter: 17
Q433:
In a 3-bus SRC implementation, what is bus 'C' used for?
A. Reading from memory
B. Writing to memory
C. Writing to registers
D. Executing instructions
Correct Answer:
C
Chapter: 17
Q434:
Which of the following steps happens in time step T1 during instruction fetch?
A. MAR receives the value of the PC
B. Instruction is executed
C. The value of PC is incremented by 2
D. Memory word is indexed by the MAR
Correct Answer:
A
Chapter: 17
Q435:
In a soft reset, which component is initialized in the SRC?
A. PC only
B. General Registers only
C. Interrupt flags only
D. PC and General Registers
Correct Answer:
A
Chapter: 17
Q436:
What does a hard reset initialize in the SRC?
A. Only the program counter (PC)
B. General registers and program counter
C. Condition code register
D. Memory registers
Correct Answer:
B
Chapter: 17
Q437:
The instruction 'sub ra, rb, rc' in a 3-bus implementation results in:
A. Addition of rb and rc
B. Subtraction of rc from rb
C. Multiplication of ra and rb
D. Division of rc by ra
Correct Answer:
B
Chapter: 17
Q438:
What does the exception vector contain?
A. Address of the interrupting process
B. The data being interrupted
C. The address of the exception handler
D. The reason for the exception
Correct Answer:
C
Chapter: 17
Q439:
Which of the following is an external exception?
A. Machine Check
B. Instruction Access Exception
C. Privileged Instruction Exception
D. Trace Exception
Correct Answer:
A
Chapter: 17
Q440:
What happens in step T2 of instruction execution?
A. PC is initialized
B. Memory data is transferred to the instruction register
C. General registers are reset
D. Interrupt flags are cleared
Correct Answer:
B