Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 17
Q441:
The primary purpose of a reset exception is:
A. To stop all instruction execution
B. To clear condition code registers
C. To save the system state
D. To set the PC to a predefined value
Correct Answer:
D
Chapter: 17
Q442:
What does the behavioral RTL for SRC reset add?
A. Initialization of the PC only
B. Control of instruction fetch
C. A check for the reset signal on each clock cycle
D. Control signals to clear memory
Correct Answer:
C
Chapter: 17
Q443:
In a machine exception, what does the processor typically save before handling the exception?
A. The status of the general registers
B. The program counter
C. The instruction register
D. The contents of memory
Correct Answer:
B
Chapter: 17
Q444:
External exceptions like keyboard or mouse inputs are typically:
A. Synchronous
B. Asynchronous
C. Programmed
D. Maskable
Correct Answer:
B
Chapter: 17
Q445:
What does the term 'nonmaskable exception' refer to?
A. High-priority exceptions that cannot be suppressed
B. Exceptions that occur randomly
C. Low-priority exceptions that can be ignored
D. Software interrupts
Correct Answer:
A
Chapter: 17
Q446:
Machine exceptions are caused by:
A. Errors in instruction fetch
B. Issues with the memory
C. Incorrect register values
D. Programming errors
Correct Answer:
B
Chapter: 17
Q447:
What is an example of a hardware exception?
A. Illegal instruction
B. Timer reaching zero
C. Interrupt flag clear
D. PC reinitialization
Correct Answer:
B
Chapter: 17
Q448:
During an exception, what is used to identify the interrupting device?
A. Information register
B. Memory buffer
C. Program counter
D. Data register
Correct Answer:
A
Chapter: 17
Q449:
How does the 8086 processor respond to a reset instruction?
A. It restarts execution from the first instruction
B. It initializes the PC to FFFF0H
C. It halts all operations
D. It clears all registers
Correct Answer:
B
Chapter: 17
Q450:
The difference between a soft reset and a hard reset is:
A. A hard reset clears the PC only
B. A soft reset clears more state registers
C. A soft reset clears the PC and interrupt flags, while a hard reset clears all state registers
D. A hard reset clears memory, while a soft reset clears interrupts
Correct Answer:
C
Chapter: 17
Q451:
Exceptions that occur during the decoding of an instruction are called:
A. Hardware exceptions
B. Program exceptions
C. Trace exceptions
D. Nonmaskable exceptions
Correct Answer:
B
Chapter: 17
Q452:
Fill in the blank: A 3-bus implementation includes two buses for reading (A and B) and one for ______.
A. writing
B. reading
C. loading
D. storing
Correct Answer:
A
Chapter: 17
Q453:
Fill in the blank: Exceptions that are triggered by hardware events like power loss are called ______ exceptions.
A. maskable
B. nonmaskable
C. program
D. synchronous
Correct Answer:
B
Chapter: 18
Q454:
What does a pipelined processor do?
A. Executes instructions one by one
B. Issues new instruction before previous completes
C. Issues instructions sequentially
D. Delays execution of all instructions
Correct Answer:
B
Chapter: 18
Q455:
What stage comes after the Instruction Fetch in a pipelined processor?
A. Instruction Decode
B. Memory Access
C. Register Write
D. ALU Operation
Correct Answer:
A
Chapter: 18
Q456:
In the ALU2 operation stage, what is the primary function?
A. Fetch operands
B. Perform memory access
C. Perform arithmetic or logic operation
D. Write result to register
Correct Answer:
C
Chapter: 18
Q457:
What is the full form of ALSU?
A. Arithmetic Logic Shift Unit
B. Arithmetic Logical Storage Unit
C. Array Logic Shift Unit
D. Arithmetic Load Shift Unit
Correct Answer:
A
Chapter: 18
Q458:
What happens during a pipeline stall?
A. Instructions are blocked from entering
B. Data is forwarded
C. Data is processed faster
D. None of the above
Correct Answer:
A
Chapter: 18
Q459:
Data forwarding in a pipeline solves which problem?
A. Load delay
B. Data dependence
C. Branch delay
D. None of the above
Correct Answer:
B
Chapter: 18
Q460:
Which instruction is used to enable exceptions in SRC processors?
A. svi
B. edi
C. een
D. ri
Correct Answer:
C