Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 19
Q481:
If the load signal is not activated, which value is transferred to Z5?
A. Memory data
B. ALU result
C. PC value
D. Register ra
Correct Answer:
B
Chapter: 19
Q482:
Which signal decides the input for Y3 in the SRC pipeline?
A. Mp1
B. Mp3
C. Mp4
D. Mp5
Correct Answer:
C
Chapter: 19
Q483:
ALU instructions in SRC involve which types of operands?
A. Constant and Memory
B. Register and Constant
C. PC value and Memory
D. Register and Program Counter
Correct Answer:
B
Chapter: 19
Q484:
In pipelined SRC, what does Mp3 control?
A. Memory access
B. Operand 1
C. PC value
D. Operand 2
Correct Answer:
D
Chapter: 19
Q485:
Branch instructions calculate target addresses based on which register?
A. R[ra]
B. R[rb]
C. R[rc]
D. PC
Correct Answer:
B
Chapter: 19
Q486:
Fill in the blank: The condition for branch instructions is evaluated using ____ in the SRC pipeline.
A. IR bits
B. PC bits
C. Opcode bits
D. Register rc value
Correct Answer:
D
Chapter: 19
Q487:
Fill in the blank: During memory access stage in a load instruction, data is stored in ____.
A. Y3
B. Z4
C. Memory
D. Register ra
Correct Answer:
C
Chapter: 20
Q488:
What is the purpose of data forwarding in a pipeline?
A. To eliminate memory access
B. To avoid structural hazards
C. To resolve data hazards
D. To increase instruction speed
Correct Answer:
C
Chapter: 20
Q489:
Which of the following is NOT a type of hazard in pipelining?
A. Data hazard
B. Control hazard
C. Register hazard
D. Structural hazard
Correct Answer:
C
Chapter: 20
Q490:
What is the minimum dependence distance required for a load instruction to avoid hazards?
A. 2 cycles
B. 3 cycles
C. 4 cycles
D. 5 cycles
Correct Answer:
A
Chapter: 20
Q491:
When is a branch hazard likely to occur?
A. When two instructions share a memory resource
B. When a branch instruction modifies the PC
C. When the ALU performs a subtraction
D. When data is forwarded incorrectly
Correct Answer:
B
Chapter: 20
Q492:
Which hazard occurs when the same resource is accessed in different ways simultaneously?
A. Data hazard
B. Structural hazard
C. Branch hazard
D. Operand hazard
Correct Answer:
B
Chapter: 20
Q493:
The instruction following a branch instruction is always executed. This is called ___.
A. Branch delay slot
B. NOP slot
C. Pipeline stall
D. Forwarding slot
Correct Answer:
A
Chapter: 20
Q494:
A structural hazard occurs when:
A. Two instructions share the same resource
B. Data is written before being read
C. A branch modifies the program counter
D. Data is forwarded incorrectly
Correct Answer:
A
Chapter: 20
Q495:
In the following code, what hazard exists between the two instructions? 200: add r2, r3, r4; 204: sub r7, r2, r6
A. Branch hazard
B. Data hazard
C. Structural hazard
D. Control hazard
Correct Answer:
B
Chapter: 20
Q496:
Data forwarding can be used to resolve hazards at which pipeline stages?
A. Stage 1 and 2
B. Stage 2 and 3
C. Stage 3 and 4
D. Stage 3 and 5
Correct Answer:
D
Chapter: 20
Q497:
In the instruction 200: shl r6, r3, 2, what type of operation is performed?
A. Arithmetic operation
B. Logical operation
C. Shift operation
D. Memory operation
Correct Answer:
C
Chapter: 20
Q498:
Fill in the blank: The compiler may insert a ________ instruction to handle branch hazards.
A. add
B. nop
C. sub
D. load
Correct Answer:
B
Chapter: 20
Q499:
Which of the following instructions could introduce a RAW (read after write) data hazard?
A. add r1, r2, r3
B. sub r4, r5, r6
C. ld r7, [4(r5)]
D. str r4, 56
Correct Answer:
A
Chapter: 20
Q500:
In pipeline RTL, what does the expression pause2, pause1, op3 0 indicate?
A. A memory access stall
B. A branch prediction failure
C. A pipeline bubble
D. Data forwarding failure
Correct Answer:
C