Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Chapter: 43
Q881:
How is memory expanded if a microprocessor requires more address space than initially available?
A. By adding more RAM chips
B. By increasing the data bus width
C. By reducing the address bus width
D. By upgrading the ROM size
Correct Answer:
A
Chapter: 43
Q882:
How does memory expansion affect the number of addressable locations?
A. Increasing address lines increases locations
B. Increasing data lines increases locations
C. Adding more RAM chips increases locations
D. Reducing address lines decreases locations
Correct Answer:
A
Chapter: 43
Q883:
What is the function of an address decoder in memory systems?
A. To select the appropriate memory chip
B. To manage data transfer rates
C. To enhance memory speed
D. To increase address bus width
Correct Answer:
A
Chapter: 43
Q884:
How does a 2 x 4 decoder select memory chips based on address lines?
A. Uses the least significant address lines
B. Uses the most significant address lines
C. Uses both high and low address lines
D. Connects all address lines together
Correct Answer:
B
Chapter: 43
Q885:
How are two 4K Byte RAM chips used to form an 8K Byte memory?
A. Connected in parallel
B. Connected in series
C. Address lines are split
D. Data lines are combined
Correct Answer:
C
Chapter: 43
Q886:
What is the advantage of using FPGA over a Programmable Logic Device (PLD)?
A. More flexible logic blocks
B. Less power consumption
C. Easier to program
D. Smaller size
Correct Answer:
A
Chapter: 43
Q887:
In a 1 MByte memory map, what is the purpose of having vacant memory blocks?
A. For future expansion
B. To reduce memory size
C. To store ROM data
D. To store data buffers
Correct Answer:
A
Chapter: 43
Q888:
What is the key difference between SRAM and DRAM in terms of memory implementation?
A. SRAM uses latches, DRAM uses capacitors
B. SRAM is volatile, DRAM is non-volatile
C. SRAM requires refresh cycles, DRAM does not
D. SRAM is slower, DRAM is faster
Correct Answer:
A
Chapter: 44
Q889:
What does a Karnaugh Map help to simplify in Boolean algebra?
A. Logic gates
B. Boolean expressions
C. Arithmetic operations
D. Digital circuits
Correct Answer:
B
Chapter: 44
Q890:
How many cells are there in a 3-variable Karnaugh Map?
A. 4
B. 8
C. 16
D. 32
Correct Answer:
B
Chapter: 44
Q891:
Each Logic Block consists of how many Logic elements?
A. One
B. Two
C. Three
D. Four
Correct Answer:
D
Chapter: 44
Q892:
What is the primary function of the Look-Up Table (LUT) in a Logic Element?
A. Logic function generator
B. Analog signal processing
C. Data storage
D. Voltage regulation
Correct Answer:
A
Chapter: 44
Q893:
How many inputs does the Look-Up Table (LUT) have in a Logic Element?
A. 2
B. 3
C. 4
D. 5
Correct Answer:
C
Chapter: 44
Q894:
The voltage gain of the Inverting Amplifier is given by the relation ________
A. Vout / Vin = - Rf / Ri
B. Vout / Rf = - Vin / Ri
C. Rf / Vin = - Ri / Vout
D. Rf / Vin = Ri / Vout
Correct Answer:
A
Chapter: 44
Q895:
LUT is acronym for _________
A. Look Up Table
B. Local User Terminal
C. Least Upper Time Period
D. None of given options
Correct Answer:
A
Chapter: 0
Q896:
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?
A. 2
B. 4
C. 6
D. 8
Correct Answer:
D
Chapter: 0
Q897:
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.
A. 1110
B. 111
C. 1000
D. 1001
Correct Answer:
C
Chapter: 0
Q898:
If the FIFO Memory output is already filled with data then ________
A. It is locked; no data is allowed to enter
B. It is not locked; the new data overwrites the previous data.
C. Previous data is swapped out of memory and new data enters
D. None of given options
Correct Answer:
C
Chapter: 44
Q899:
The process of converting the analogue signal into a digital representation (code) is known as ___________
A. Strobing
B. Amplification
C. Quantization
D. Digitization
Correct Answer:
C
Chapter: 44
Q900:
In a LUT configured as a full-adder, how many memory locations are used to represent Sum and Cout?
A. 8
B. 4
C. 16
D. 12
Correct Answer:
A