Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Chapter: 40
Q821:
How is a memory address split in a large memory?
A. Into data and control lines
B. Into row and column addresses
C. Into high and low bits
D. Into even and odd addresses
Correct Answer:
B
Chapter: 40
Q822:
What manages the control of Data In and Data Out lines in a memory circuit?
A. Address Decoder
B. Row Decoder
C. Input/Output Buffer
D. Column Decoder
Correct Answer:
C
Chapter: 40
Q823:
Which signal needs to be active to write data into a memory?
A. OE (Output Enable)
B. CS (Chip Select)
C. W (Write)
D. R (Read)
Correct Answer:
C
Chapter: 40
Q824:
During a Memory Write Cycle, what must remain stable for the write pulse width?
A. Address signals
B. Data signals
C. Control signals
D. Clock signals
Correct Answer:
A
Chapter: 40
Q825:
What controls the sequence of signals for reading and writing data in memory?
A. Clock signals
B. Read/Write Cycle
C. Address signals
D. Control signals
Correct Answer:
B
Chapter: 40
Q826:
What type of memory is synchronized with a clock signal?
A. Asynchronous RAM
B. Static RAM
C. Synchronous Burst SRAM
D. Dynamic RAM
Correct Answer:
C
Chapter: 40
Q827:
What is the advantage of Synchronous Burst SRAM over Asynchronous SRAM?
A. Lower power consumption
B. Higher density
C. Faster operation
D. Simpler design
Correct Answer:
C
Chapter: 40
Q828:
In Synchronous SRAM, what happens during a positive clock transition?
A. Data is stored in memory
B. Data is read from memory
C. Signals are latched into registers
D. Address lines are refreshed
Correct Answer:
C
Chapter: 40
Q829:
What feature does the Synchronous SRAM have for accessing multiple memory locations?
A. Multi-bit addressing
B. Burst operation
C. Parallel access
D. Dual port
Correct Answer:
B
Chapter: 40
Q830:
What does the Burst Logic circuitry do in a Synchronous SRAM?
A. Reduces power consumption
B. Increments addresses automatically
C. Decreases memory access time
D. Synchronizes data transfer
Correct Answer:
B
Chapter: 40
Q831:
How many locations can Synchronous SRAM access in one burst operation?
A. 1
B. 2
C. 3
D. 4
Correct Answer:
D
Chapter: 40
Q832:
What is the main difference between Static RAM and Dynamic RAM?
A. DRAM uses a latch for storage
B. SRAM uses a capacitor for storage
C. DRAM uses a capacitor for storage
D. SRAM requires periodic refreshing
Correct Answer:
C
Chapter: 40
Q833:
What is the main drawback of Dynamic RAM (DRAM)?
A. High power consumption
B. Requires more transistors
C. Requires periodic refreshing
D. Higher cost
Correct Answer:
C
Chapter: 40
Q834:
What happens during the Refresh Cycle in a DRAM?
A. Data is written to memory
B. Data is read from memory
C. The capacitor is recharged
D. The MOSFET is activated
Correct Answer:
C
Chapter: 40
Q835:
What technique is used by DRAM to reduce the number of address lines?
A. Address multiplexing
B. Clock synchronization
C. Parallel addressing
D. Serial communication
Correct Answer:
A
Chapter: 40
Q836:
What signals are used to latch the row and column addresses in DRAM?
A. CS and OE
B. RAS and CAS
C. WE and OE
D. DIN and DOUT
Correct Answer:
B
Chapter: 40
Q837:
How is a single memory location accessed in a DRAM?
A. By selecting the entire memory array
B. By selecting a row and a column
C. By selecting all columns
D. By activating all address lines
Correct Answer:
B
Chapter: 40
Q838:
What component selects the row and column in a DRAM?
A. Address Register
B. Input/Output Buffer
C. Data Selector
D. Row and Column Decoders
Correct Answer:
D
Chapter: 40
Q839:
How is data read from a DRAM cell?
A. By refreshing the capacitor
B. By charging the MOSFET
C. By reading from the Output Buffer
D. By activating the Write signal
Correct Answer:
C
Chapter: 40
Q840:
During a DRAM refresh cycle, what happens to the memory cells?
A. All cells are deactivated
B. All cells are rewritten
C. All cells are refreshed
D. All cells are cleared
Correct Answer:
C