Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Multiple Choice Questions
Q501: How does the SRC pipeline resolve data hazards?
- A: Using NOP instructions
- B: By stalling
- C: By using data forwarding
- D: Both B and C
View Answer
D
Q502: The instruction alu3&alu2&((ra3=rb2)~((ra3=rc2)&!imm2)) in RTL detects:
- A: A branch hazard
- B: A structural hazard
- C: A data hazard
- D: A memory access error
View Answer
C
Q503: Which instruction does NOT access memory in the pipeline cycle?
- A: Add
- B: Load
- C: Store
- D: Branch
View Answer
A
Q504: The result of an ALU operation is typically available at which stage?
- A: Stage 1
- B: Stage 2
- C: Stage 3
- D: Stage 4
View Answer
C
Q505: Fill in the blank: Data forwarding transfers data from stage 3 to stage ____.
- A: Stage 1
- B: Stage 2
- C: Stage 4
- D: Stage 5
View Answer
B
Q506: What is Instruction Level Parallelism?
- A: Executing multiple instructions in a sequence
- B: Executing multiple instructions in parallel
- C: Executing one instruction per clock cycle
- D: None of the above
View Answer
B
Q507: Which of the following is a feature of Superscalar Architecture?
- A: Only one functional unit
- B: One instruction executed at a time
- C: Multiple instructions executed in parallel
- D: Single pipeline
View Answer
C
Q508: In pipelining, how are instructions executed?
- A: Sequentially
- B: In parallel
- C: Overlapped in different stages
- D: In reverse order
View Answer
C
Q509: What is the purpose of the Branch Prediction Unit (BPU)?
- A: To decode instructions
- B: To predict branch target addresses
- C: To manage data forwarding
- D: To handle floating-point operations
View Answer
B
Q510: Which of the following architectures uses very long instruction words?
- A: Superscalar
- B: Pipelined
- C: VLIW
- D: RISC
View Answer
C