Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Multiple Choice Questions
Q471: Which of the following instructions could cause a load delay?
- A: add r3, r2, r1
- B: load r2, 34(r1)
- C: sub r4, r5, r3
- D: mov r1, r2
View Answer
B
Q472: What is the time required to process a single instruction called?
- A: Latency
- B: Throughput
- C: Execution time
- D: Pipeline stall
View Answer
A
Q473: In a non-pipelined machine, how many cycles are required to complete one instruction?
- A: 1
- B: 3
- C: 5
- D: 10
View Answer
C
Q474: What happens in the memory access stage of the pipeline?
- A: Read from memory
- B: Write to memory
- C: Both A and B
- D: Neither A nor B
View Answer
C
Q475: What are the stages of the SRC pipeline?
- A: Instruction Fetch, ALU, Memory Access
- B: Instruction Decode, ALU, Branches
- C: Instruction Fetch, ALU, Register
- D: Instruction Fetch, ALU, Memory
View Answer
A
Q476: In a pipelined SRC, which register holds the fetched instruction?
- A: IR1
- B: IR2
- C: IR3
- D: IR4
View Answer
B
Q477: What does X3 in the pipeline store during ALU instruction execution?
- A: Constant from instruction
- B: Operand value from memory
- C: Operand value from register file
- D: Operand value from PC
View Answer
C
Q478: Which register holds the result of the ALU operation?
- A: X3
- B: Y3
- C: Z4
- D: Z5
View Answer
C
Q479: In which stage does register Z5 hold the value for writing back?
- A: Instruction Fetch
- B: Memory Access
- C: Write-back
- D: ALU Operation
View Answer
C
Q480: What does Mp1 control in the pipeline?
- A: ALU operations
- B: Memory access
- C: PC input
- D: Register write-back
View Answer
C