Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Multiple Choice Questions
Q461: In the RTL, what does the instruction rfi (Return from Interrupt) do?
- A: Disables interrupt
- B: Enables exception
- C: Returns from an interrupt
- D: Saves instruction execution state
View Answer
C
Q462: What does pipelining improve in terms of processor performance?
- A: Latency
- B: Efficiency
- C: Throughput
- D: Memory access speed
View Answer
C
Q463: In which stage of a pipeline does memory access happen?
- A: Instruction fetch
- B: ALU operation
- C: Memory access
- D: Register write
View Answer
C
Q464: Which of the following is NOT a complication in pipelining?
- A: Data dependence
- B: Branch delay
- C: Load delay
- D: Register write stalls
View Answer
D
Q465: Pipelining affects which of the following?
- A: Latency
- B: Instruction execution speed
- C: Instruction set
- D: Throughput
View Answer
D
Q466: Which instruction in the pipeline might need to be stalled due to data dependence?
- A: load r2, 34(r1)
- B: add r3, r2, r1
- C: sub r4, r5, r3
- D: mov r1, r2
View Answer
B
Q467: What method is used to resolve branch delay in pipelining?
- A: NOP instruction
- B: Data forwarding
- C: ALU stalls
- D: Memory access stalls
View Answer
A
Q468: In which stage of the pipeline is the instruction fetched from memory?
- A: Instruction decode
- B: ALU operation
- C: Instruction fetch
- D: Register write
View Answer
C
Q469: What is the main advantage of separating instruction memory and data memory in a pipeline?
- A: Decreases latency
- B: Improves throughput
- C: Prevents pipeline stalls
- D: Allows instructions to be fetched while data is loaded
View Answer
D
Q470: Fill in the blank: Data forwarding allows the result from the ______ stage to be transferred directly to the decode stage of the next instruction.
- A: Memory access
- B: Instruction fetch
- C: Execute
- D: Register write
View Answer
C