Important Digital Logic and Design Short Questions
Chapter: 23
Question 1:
How does a positive edge-triggered flip-flop operate?
Answer:
A positive edge-triggered flip-flop changes its output state on the low-to-high transition of the clock signal.
Chapter: 23
Question 2:
What is the effect of J=0 and K=1 on a J-K flip-flop?
Answer:
When J=0 and K=1, the J-K flip-flop is reset, resulting in Q=0 and Q=1 regardless of its previous state.
Chapter: 23
Question 3:
Explain the function of asynchronous preset and clear inputs in flip-flops.
Answer:
Asynchronous preset and clear inputs allow the flip-flop to be set or cleared to a known state independently of the clock signal.
Chapter: 23
Question 4:
How does the master-slave flip-flop differ from edge-triggered flip-flops?
Answer:
The master-slave flip-flop has two stages that work in different halves of the clock cycle, whereas edge-triggered flip-flops change state based on clock edges.
Chapter: 24
Question 5:
What is the primary advantage of using edge-triggered D flip-flops over gated D-latches in data storage?
Answer:
Edge-triggered D flip-flops store data precisely at the clock transition, ensuring stable data storage even if input data changes after the clock transition. Gated D-latches can be affected by changes in input data during enable time.
Chapter: 24
Question 6:
How does a D flip-flop synchronize asynchronous inputs?
Answer:
A D flip-flop synchronizes asynchronous inputs by sampling the input at clock edges, which ensures that the output is stable and reflects complete clock pulses, avoiding glitches or partial pulses.
Chapter: 24
Question 7:
What is the role of a register in a microprocessor?
Answer:
A register in a microprocessor is a multi-bit flip-flop used to store, exchange, or copy data. Registers allow simultaneous latching of multi-bit input data through synchronized clock signals.
Chapter: 24
Question 8:
What happens when both J and K inputs of a J-K flip-flop are set to 0?
Answer:
When J = 0 and K = 0, the J-K flip-flop maintains its previous state. The outputs Q and Q remain unchanged regardless of the clock transitions.
Chapter: 24
Question 9:
How does a J-K flip-flop function when J = 0 and K = 1?
Answer:
When J = 0 and K = 1, the J-K flip-flop resets the output to Q = 0 and Q = 1 on a clock transition, regardless of the previous state.
Chapter: 24
Question 10:
What is the result of having J = 1 and K = 0 in a J-K flip-flop?
Answer:
When J = 1 and K = 0, the J-K flip-flop sets its output to Q = 1 and Q = 0 on a clock transition, irrespective of the previous state.