Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Chapter: 0
Q181:
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.
A. Undefined
B. One
C. Zero
D. No Output as input is invalid.
Correct Answer:
C
Chapter: 0
Q182:
________ is invalid number of cells in a single group formed by the adjacent cells in K-map
A. 2
B. 8
C. 12
D. 16
Correct Answer:
C
Chapter: 182
Q183:
The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder.
A. AND
B. OR
C. NOT
D. XOR
Correct Answer:
A
Chapter: 235
Q184:
___________ is one of the examples of asynchronous inputs.
A. J-K input
B. S-R input
C. D input
D. Clear Input (CLR)
Correct Answer:
D
Chapter: 0
Q185:
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
A. zero
B. 1101
C. 1011
D. 1111
Correct Answer:
C
Chapter: 217
Q186:
A flip-flop with no clock input, can be used for _________
A. Asynchronous control
B. Synchronous control
C. Synchronizing inputs
D. Counting
Correct Answer:
A
Chapter: 91
Q187:
The term “Open Collector” is used in the context of ________
A. Output
B. Input
C. Memory
D. Data transfer
Correct Answer:
A
Chapter: 397
Q188:
The address from which the data is read, is provided by _______
A. Depends on circuitry
B. None of given options
C. RAM
D. Microprocessor
Correct Answer:
D
Chapter: 424
Q189:
FIFO is an acronym for __________
A. First In, First Out
B. Fly in, Fly Out
C. Fast in, Fast Out
D. None of given options
Correct Answer:
A
Chapter: 460
Q190:
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output.
A. Resolution
B. Accuracy
C. Quantization
D. Missing Code
Correct Answer:
B
Chapter: 270
Q191:
Above is the circuit diagram of _______.
A. Asynchronous up-counter
B. Asynchronous down-counter
C. Synchronous up-counter
D. Synchronous down-counter
Correct Answer:
A
Chapter: 354
Q192:
The sequence of states that are implemented by a n-bit Johnson counter is
A. n+2 (n plus 2)
B. 2n (n multiplied by 2)
C. 2^n (2 raise to power n)
D. n^2 (n raise to power 2)
Correct Answer:
B
Chapter: 72
Q193:
"A + B = B + A" is __________
A. Demorgan‟s Law
B. Distributive Law
C. Commutative Law
D. Associative Law
Correct Answer:
C
Chapter: 155
Q194:
An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is _______
A. Using a single comparator
B. Using Iterative Circuit based Comparators
C. Connecting comparators in vertical hierarchy
D. Extra logic gates are always required
Correct Answer:
B
Chapter: 178
Q195:
Demultiplexer is also called
A. Data selector
B. Data router
C. Data distributor
D. Data encoder
Correct Answer:
C
Chapter: 242
Q196:
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is
A. 10 mW
B. 25 mW
C. 64 mW
D. 1024
Correct Answer:
B
Chapter: 269
Q197:
____________ counters as the name indicates are not triggered simultaneously.
A. Asynchronous
B. Synchronous
C. Positive-Edge triggered
D. Negative-Edge triggered
Correct Answer:
A
Chapter: 281
Q198:
A synchronous decade counter will have _______ flip-flops
A. 3
B. 4
C. 7
D. 10
Correct Answer:
B
Chapter: 341
Q199:
________ is used to minimize the possible no. of states of a circuit.
A. State assignment
B. State reduction
C. Next state table
D. State diagram
Correct Answer:
A
Chapter: 356
Q200:
The alternate solution for a demultiplexer-register combination circuit is _________
A. Parallel in / Serial out shift register
B. Serial in / Parallel out shift register
C. Parallel in / Parallel out shift register
D. Serial in / Serial Out shift register
Correct Answer:
B