Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 36
Q821:
In floating-point addition, the last step is to:
A. Normalize the sum
B. Round off the result
C. Check for overflow
D. Unpack the fields
Correct Answer:
C
Chapter: 37
Q822:
What does the memory address register (MAR) contain?
A. Data word
B. Memory address
C. Control signals
D. Request signal
Correct Answer:
B
Chapter: 37
Q823:
The memory buffer register (MBR) is directly connected to the _______.
A. Address bus
B. Data bus
C. Control signals
D. CPU
Correct Answer:
B
Chapter: 37
Q824:
How many bits does a typical memory address range from 0 to?
A. 2m-1
B. 2^m-1
C. 2m
D. 2^(m-1)
Correct Answer:
B
Chapter: 37
Q825:
The register file contains how many 32-bit wide registers?
A. 16
B. 32
C. 64
D. 128
Correct Answer:
B
Chapter: 37
Q826:
When the REQUEST signal is high, it corresponds to a ______ operation.
A. Read
B. Write
C. Reset
D. Idle
Correct Answer:
A
Chapter: 37
Q827:
In the 1×8 Memory Cell Array, which signal is common to all cells?
A. Select
B. DataIn
C. DataOut
D. Read/Write
Correct Answer:
A
Chapter: 37
Q828:
The 4×8 Memory Cell Array arrangement is described as being in ______ dimensions.
A. One
B. Two
C. Three
D. Four
Correct Answer:
B
Chapter: 37
Q829:
The 64k×1 Static RAM Chip requires how many address lines?
A. 8
B. 16
C. 32
D. 64
Correct Answer:
B
Chapter: 37
Q830:
In a read operation of the SRAM cell, the data becomes available on the data bus after ______.
A. Time "tAA"
B. Time "tWR"
C. Time "tAA" + "tWR"
D. Immediately
Correct Answer:
A
Chapter: 37
Q831:
The write signal for SRAM must be held valid for a minimum time interval known as ______.
A. tWR
B. tAA
C. tRAS
D. tRCD
Correct Answer:
A
Chapter: 37
Q832:
In a DRAM cell, the storage capacitor needs to be refreshed every ______ ms.
A. 45293
B. 45397
C. 20-30
D. 60-70
Correct Answer:
B
Chapter: 37
Q833:
A typical one-level decoder has how many outputs?
A. n
B. 2n
C. 3n
D. 4n
Correct Answer:
B
Chapter: 37
Q834:
What type of memory uses a charge on a capacitor for data storage?
A. SRAM
B. DRAM
C. Flash
D. Cache
Correct Answer:
B
Chapter: 37
Q835:
The chip select line (CS) is essential in both SRAM and ______ operations.
A. Write
B. Reset
C. Idle
D. Read
Correct Answer:
A
Chapter: 37
Q836:
What operation does the select signal enable in a memory cell?
A. Write only
B. Read/Write
C. DataIn only
D. DataOut only
Correct Answer:
B
Chapter: 37
Q837:
The lower order address lines in a 64k×1 Static RAM Chip select how many bits?
A. 8
B. 16
C. 256
D. 64
Correct Answer:
D
Chapter: 37
Q838:
Fill in the blank: In a 4×8 memory cell array, two address bits A0 and A1 are decoded into ______ select lines.
A. 2
B. 4
C. 8
D. 16
Correct Answer:
B
Chapter: 37
Q839:
Fill in the blank: Dynamic RAM is also known as ______ memory.
A. Static
B. Volatile
C. Non-volatile
D. Persistent
Correct Answer:
B
Chapter: 38
Q840:
What type of memory can be written into only once?
A. Read Only Memory (ROM)
B. Programmable Read Only Memory (PROM)
C. Electrically Erasable Programmable Read-Only Memory (EEPROM)
D. Dynamic RAM
Correct Answer:
B