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Advanced Computer Architecture MCQs with Answers

Practice important Advanced Computer Architecture MCQs with answers and explanations.

Chapter: 31
Q721:
In which DMA configuration does the DMA and I/O modules connect through an I/O bus?
A. Single Bus Detached DMA
B. Single Bus Integrated DMA
C. I/O Bus
D. Integrated Bus Configuration
Correct Answer: C
Chapter: 31
Q722:
What does the DMA Controller (DMAC) do during a DMA transfer?
A. It processes all CPU instructions
B. It manages bus control
C. It manages memory allocation
D. It performs data encoding
Correct Answer: B
Chapter: 31
Q723:
The instruction load [2], [9] is considered illegal because:
A. It requires two steps
B. It requires more than one CPU
C. It transfers directly between peripherals
D. It involves too many memory locations
Correct Answer: A
Chapter: 31
Q724:
What is the role of the CPU in a DMA transfer?
A. To manage all I/O requests
B. To act as a middleman for data transfers
C. To handle interrupts during data transfer
D. To send DMA requests
Correct Answer: B
Chapter: 31
Q725:
What is the purpose of the Bus Grant pulse in the DMA process?
A. To release bus control
B. To request data transfer
C. To indicate the start of a DMA cycle
D. To confirm data transfer
Correct Answer: C
Chapter: 31
Q726:
In which DMA configuration does the DMA controller not share the system bus with the CPU?
A. Single Bus Detached DMA
B. Single Bus Integrated DMA
C. I/O Bus
D. Integrated Bus Configuration
Correct Answer: A
Chapter: 31
Q727:
During a DMA transfer, which bus control technique allows the CPU to pause operations?
A. Cycle Stealing
B. Bus Arbitration
C. Direct Control
D. Interrupt Management
Correct Answer: A
Chapter: 31
Q728:
What percentage of CPU time is spent handling DMA requests in the example with a 500 MHz processor?
A. 0.1
B. 0.025
C. 0.004
D. 0.001
Correct Answer: B
Chapter: 31
Q729:
In an I/O channel, what is a key capability?
A. To manage all memory requests
B. To execute instructions without CPU involvement
C. To provide high-speed data transfers
D. To connect multiple CPUs
Correct Answer: B
Chapter: 31
Q730:
Which type of multiplexer channel is used for high-speed devices?
A. Byte Multiplexer
B. Block Multiplexer
C. Byte Stream Multiplexer
D. Block Stream Multiplexer
Correct Answer: B
Chapter: 31
Q731:
The physical address is the address in which part of the system?
A. CPU cache
B. Memory
C. Virtual space
D. DMA controller
Correct Answer: B
Chapter: 31
Q732:
What happens to CPU performance when using a cache during DMA transfers?
A. It decreases due to infrequent access
B. It increases due to efficient access
C. It remains unchanged
D. It is dependent on the DMA controller
Correct Answer: A
Chapter: 31
Q733:
The terms "simplex" and "duplex" refer to what aspect of data communication?
A. Speed of transmission
B. Direction of data flow
C. Quality of data transfer
D. Encryption methods
Correct Answer: B
Chapter: 32
Q734:
What is the main function of a hard disk in a computer system?
A. Data storage
B. Data processing
C. Networking
D. Graphics rendering
Correct Answer: A
Chapter: 32
Q735:
A hard disk consists of a set of ________.
A. Sectors
B. Platters
C. Heads
D. Controllers
Correct Answer: B
Chapter: 32
Q736:
Each platter of a hard disk is divided into tracks, which are further divided into ________.
A. Sectors
B. Bytes
C. Blocks
D. Chunks
Correct Answer: A
Chapter: 32
Q737:
The time taken for the head to move to a specific track is known as ________.
A. Rotational delay
B. Seek time
C. Transfer time
D. Overhead time
Correct Answer: B
Chapter: 32
Q738:
What is the average rotational latency if a disk rotates at 20,000 rpm?
A. 1.5 ms
B. 0.5 ms
C. 5 ms
D. 10 ms
Correct Answer: A
Chapter: 32
Q739:
If a magnetic disk has an average seek time of 5 ms and a transfer rate of 50 MB/sec, what is the average time to read or write 1024 bytes?
A. 6.22 ms
B. 8.22 ms
C. 10.22 ms
D. 5.22 ms
Correct Answer: B
Chapter: 32
Q740:
How is the storage capacity of a hard disk determined?
A. Number of tracks only
B. Number of platters only
C. Number of platters and tracks
D. Size of sectors
Correct Answer: C

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