Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 30
Q701:
What is the maximum number of devices a 20MIPS processor can handle with 1000 characters/second?
A. 540
B. 600
C. 500
D. 700
Correct Answer:
A
Chapter: 30
Q702:
What does the percentage of CPU time used in interrupt handling signify?
A. Processor efficiency
B. Data transfer rate
C. I/O device speed
D. Polling frequency
Correct Answer:
A
Chapter: 30
Q703:
The floppy drive uses a _______ data bus for transferring data.
A. 16-bit
B. 8-bit
C. 32-bit
D. 64-bit
Correct Answer:
A
Chapter: 30
Q704:
How often should a processor poll to match the interrupt overhead?
A. 800 times per second
B. 1000 times per second
C. 500 times per second
D. 200 times per second
Correct Answer:
A
Chapter: 30
Q705:
The main advantage of DMA is the __________ of data transfer.
A. Speed
B. Complexity
C. Cost
D. Interruption
Correct Answer:
A
Chapter: 30
Q706:
What is the consequence of using DMA in a system?
A. It requires less memory
B. It simplifies the CPU
C. It adds a DMA controller
D. It decreases transfer rates
Correct Answer:
C
Chapter: 30
Q707:
What is the transfer rate of the floppy drive in the example?
A. 25KB/sec
B. 12.5KB/sec
C. 50KB/sec
D. 100KB/sec
Correct Answer:
A
Chapter: 30
Q708:
For how long must a processor poll to maintain a 1ms delay?
A. 500 times per second
B. 100 times per second
C. 200 times per second
D. 50 times per second
Correct Answer:
A
Chapter: 30
Q709:
The average delay for an I/O request in the polling example is _______.
A. 10ms
B. 1ms
C. 5ms
D. 20ms
Correct Answer:
A
Chapter: 30
Q710:
The percentage of CPU time spent in polling for a keyboard is _______.
A. 6.0E-5
B. 0.0256
C. 0.512
D. 0.005
Correct Answer:
A
Chapter: 30
Q711:
How many cycles per second are spent handling I/O when using interrupts only?
A. 2400000
B. 3395000
C. 200000
D. 1000000
Correct Answer:
A
Chapter: 30
Q712:
What is the typical overhead incurred by a DMA operation?
A. 2000 cycles
B. 1000 cycles
C. 500 cycles
D. 5000 cycles
Correct Answer:
A
Chapter: 30
Q713:
To achieve a high data transfer rate, the CPU must ___________.
A. Stay idle
B. Continuously poll
C. Use DMA
D. Increase interrupts
Correct Answer:
C
Chapter: 31
Q714:
What is the main advantage of Direct Memory Access (DMA)?
A. Higher transfer rates
B. Lower cost
C. Increased CPU workload
D. Reduced memory usage
Correct Answer:
A
Chapter: 31
Q715:
In DMA, which component is typically the master during a bus cycle?
A. Peripheral Device
B. CPU
C. DMA Controller
D. Memory
Correct Answer:
B
Chapter: 31
Q716:
What does the term "cycle stealing" refer to in DMA?
A. The CPU taking control of the bus
B. The DMA module taking control of the bus
C. The CPU sending data
D. The DMA module ignoring requests
Correct Answer:
B
Chapter: 31
Q717:
Which of the following is NOT a DMA transfer combination?
A. Memory to memory
B. Memory to peripheral
C. Peripheral to peripheral
D. CPU to peripheral
Correct Answer:
D
Chapter: 31
Q718:
In the DMA transfer protocol, what signal does the DMA controller send to the CPU at the end of a transfer?
A. Reset signal
B. Release signal
C. Bus Grant signal
D. Interrupt signal
Correct Answer:
D
Chapter: 31
Q719:
Which step involves the DMA controller transferring the entire block of data?
A. 1st Step
B. 2nd Step
C. 3rd Step
D. Setup Step
Correct Answer:
B
Chapter: 31
Q720:
What is the main disadvantage of using DMA?
A. Low transfer rates
B. Complexity and cost
C. Slower data transfer
D. CPU overload
Correct Answer:
B