Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 10
Q321:
Fill in the blank: In the auto decrement addressing mode, the register value is first ______ and then used for memory reference.
A. incremented
B. decremented
C. cleared
D. stored
Correct Answer:
B
Chapter: 12
Q322:
What are the two main sub-systems in processor design?
A. Data path and control unit
B. ALU and memory
C. Registers and buses
D. Cache and instruction set
Correct Answer:
A
Chapter: 12
Q323:
The first step in processor design is the specification of what?
A. ALU
B. Instruction Set Architecture (ISA)
C. Control unit design
D. Data path design
Correct Answer:
B
Chapter: 12
Q324:
The unit of activity in Behavioral RTL is based on ______.
A. Register transfers
B. Instruction execution
C. Clock cycles
D. Control signals
Correct Answer:
B
Chapter: 12
Q325:
The Data Path Design involves the placement and interconnection of ______.
A. Registers and buses
B. ALU and memory
C. Control signals
D. Timing devices
Correct Answer:
A
Chapter: 12
Q326:
Which type of control unit can be designed for processors?
A. Only micro-programmed
B. Only hard-wired
C. Both hard-wired and micro-programmed
D. Only register-based
Correct Answer:
C
Chapter: 12
Q327:
A uni-bus implementation of the data path is also called ______.
A. Two-bus architecture
B. Single-bus architecture
C. Multi-bus architecture
D. Hybrid-bus architecture
Correct Answer:
B
Chapter: 12
Q328:
The Memory Address Register (MAR) is responsible for ______.
A. Holding instructions
B. Holding data during transmission
C. Holding addresses of memory
D. Incrementing program counter
Correct Answer:
C
Chapter: 12
Q329:
What does the Memory Buffer Register (MBR) do?
A. Transmits data to/from memory
B. Stores next instruction
C. Increments program counter
D. Stores control signals
Correct Answer:
A
Chapter: 12
Q330:
The Instruction Register (IR) holds ______.
A. Data transferred from memory
B. Control signals
C. The current instruction
D. ALU result
Correct Answer:
C
Chapter: 12
Q331:
The Program Counter (PC) holds ______.
A. The memory address to be accessed
B. Address of next instruction
C. Register operation
D. Control signals
Correct Answer:
B
Chapter: 12
Q332:
Register A and C in the data path are used for ______.
A. Holding control signals
B. Temporary storage of operands
C. Controlling bus timing
D. Register renaming
Correct Answer:
B
Chapter: 12
Q333:
What does the ALSU (Arithmetic Logic Shift Unit) do in the data path?
A. Transfers data to memory
B. Performs arithmetic/logic operations
C. Shifts data between registers
D. Generates control signals
Correct Answer:
B
Chapter: 12
Q334:
In processor design, what is the primary purpose of the Timing Step Generator?
A. To synchronize control signals
B. To increment the Program Counter
C. To ensure correct timing of operations
D. To generate control unit signals
Correct Answer:
C
Chapter: 12
Q335:
How many general-purpose registers are in the SRC's register file?
A. 16
B. 64
C. 32
D. 128
Correct Answer:
C
Chapter: 12
Q336:
What does the Structural RTL description represent in processor design?
A. Instruction fetch phase
B. Abstract operations of CPU
C. Actual hardware implementation
D. Instruction scheduling
Correct Answer:
C
Chapter: 12
Q337:
Which component generates the control signals required for executing RTL instructions?
A. ALU
B. Control Unit
C. Program Counter
D. Timing step generator
Correct Answer:
B
Chapter: 12
Q338:
The structural RTL for instruction fetch takes how many time steps?
A. 2
B. 3
C. 4
D. 5
Correct Answer:
B
Chapter: 12
Q339:
The sub instruction 'sub ra, rb, rc' takes how many timing steps in execution?
A. 2
B. 4
C. 3
D. 6
Correct Answer:
C
Chapter: 12
Q340:
In the add instruction 'add ra, rb, rc', what is the final time step where the result is stored?
A. T3
B. T4
C. T5
D. T6
Correct Answer:
C