Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Multiple Choice Questions
Q831: How many locations can Synchronous SRAM access in one burst operation?
- A: 1
- B: 2
- C: 3
- D: 4
View Answer
D
Q832: What is the main difference between Static RAM and Dynamic RAM?
- A: DRAM uses a latch for storage
- B: SRAM uses a capacitor for storage
- C: DRAM uses a capacitor for storage
- D: SRAM requires periodic refreshing
View Answer
C
Q833: What is the main drawback of Dynamic RAM (DRAM)?
- A: High power consumption
- B: Requires more transistors
- C: Requires periodic refreshing
- D: Higher cost
View Answer
C
Q834: What happens during the Refresh Cycle in a DRAM?
- A: Data is written to memory
- B: Data is read from memory
- C: The capacitor is recharged
- D: The MOSFET is activated
View Answer
C
Q835: What technique is used by DRAM to reduce the number of address lines?
- A: Address multiplexing
- B: Clock synchronization
- C: Parallel addressing
- D: Serial communication
View Answer
A
Q836: What signals are used to latch the row and column addresses in DRAM?
- A: CS and OE
- B: RAS and CAS
- C: WE and OE
- D: DIN and DOUT
View Answer
B
Q837: How is a single memory location accessed in a DRAM?
- A: By selecting the entire memory array
- B: By selecting a row and a column
- C: By selecting all columns
- D: By activating all address lines
View Answer
B
Q838: What component selects the row and column in a DRAM?
- A: Address Register
- B: Input/Output Buffer
- C: Data Selector
- D: Row and Column Decoders
View Answer
D
Q839: How is data read from a DRAM cell?
- A: By refreshing the capacitor
- B: By charging the MOSFET
- C: By reading from the Output Buffer
- D: By activating the Write signal
View Answer
C
Q840: During a DRAM refresh cycle, what happens to the memory cells?
- A: All cells are deactivated
- B: All cells are rewritten
- C: All cells are refreshed
- D: All cells are cleared
View Answer
C