Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Multiple Choice Questions
Q561: How many unique states can a 3-bit Asynchronous counter sequence through?
- A: 4
- B: 6
- C: 8
- D: 16
View Answer
C
Q562: What is the effect of propagation delay in an Asynchronous counter?
- A: Speeds up counting
- B: Causes timing errors
- C: Reduces power consumption
- D: Increases clock frequency
View Answer
B
Q563: A decade counter is __________.
- A: Mod-3 counter
- B: Mod-5 counter
- C: Mod-8 counter
- D: Mod-10 counter
View Answer
D
Q564: ____________ is said to occur when multiple internal variables change due to change in one input variable
- A: Clock Skew
- B: Race condition
- C: Hold delay
- D: Hold and Wait
View Answer
B
Q565: What is the frequency of the output signal of a Mod-10 counter relative to the input clock signal?
- A: "1/2"
- B: "1/4"
- C: "1/10"
- D: "1/16"
View Answer
C
Q566: What does the output of a Mod-6 counter look like?
- A: Counts from 0 to 5
- B: Counts from 0 to 6
- C: Counts from 0 to 7
- D: Counts from 0 to 9
View Answer
A
Q567: How can Asynchronous counters be made to function at high clock frequencies?
- A: By increasing clock skew
- B: By reducing flip-flop delay
- C: By using synchronous counters
- D: By adding more flip-flops
View Answer
C
Q568: How is a Mod-50 counter typically implemented using 74LS93A ICs?
- A: By cascading two 74LS93As
- B: Using a single 74LS93A
- C: Using an external clock
- D: By using one flip-flop
View Answer
A
Q569: What type of signal is generated by a Mod-n counter?
- A: n times input frequency
- B: n divided by input frequency
- C: 1/nth of input clock frequency
- D: 2n times input frequency
View Answer
C
Q570: What happens when a down counter reaches its maximum count value?
- A: Resets to binary zero
- B: Continues counting
- C: Stops counting
- D: Resets to maximum count value
View Answer
D