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Digital Logic and Design MCQs with Answers

Practice important Digital Logic and Design MCQs with answers and explanations.

Multiple Choice Questions

Q541: What happens when both PRE and CLR inputs are set to 1?
  • A: Flip-flop remains unchanged
  • B: Flip-flop resets
  • C: Flip-flop presets
  • D: Clocked operation occurs
View Answer
D

Q542: What type of flip-flop is the 74HC74?
  • A: Master-Slave J-K flip-flop
  • B: Dual Positive-Edge D flip-flop
  • C: Dual Negative-Edge D flip-flop
  • D: Single Positive-Edge D flip-flop
View Answer
B

Q543: What is the main disadvantage of Master-Slave flip-flops compared to edge-triggered flip-flops?
  • A: They operate on half clock
  • B: They consume more power
  • C: They are more complex
  • D: They have longer delay
View Answer
A

Q544: What is the output of a Master-Slave flip-flop during the positive half of the clock cycle?
  • A: Changes with clock signal
  • B: Remains unchanged
  • C: Resets to zero
  • D: Presets to one
View Answer
B

Q545: What does the Propagation Delay tPLH measure?
  • A: Time from clock to output
  • B: Time from input to clock
  • C: Time from low to high output
  • D: Time from high to low output
View Answer
C

Q546: How is the Set-up Time defined for a flip-flop?
  • A: Minimum time input is held
  • B: Time between input changes
  • C: Time for input to stabilize
  • D: Time for clock to transition
View Answer
A

Q547: What is the Hold Time in a flip-flop?
  • A: Time after clock transition
  • B: Time before clock transition
  • C: Time between two clock pulses
  • D: Time between input changes
View Answer
A

Q548: What is the Maximum Clock Frequency of a flip-flop?
  • A: Highest frequency for inputs
  • B: Highest frequency for outputs
  • C: Highest reliable clock rate
  • D: Highest transition rate
View Answer
C

Q549: Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit.
  • A: AND
  • B: NAND
  • C: NOR
  • D: XNOR
View Answer
C

Q550: What determines the unstable state duration in a Mono-stable device?
  • A: Clock input
  • B: Trigger pulse
  • C: Resistor and Capacitor
  • D: Feedback loop
View Answer
C

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