Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Multiple Choice Questions
Q191: Above is the circuit diagram of _______.
- A: Asynchronous up-counter
- B: Asynchronous down-counter
- C: Synchronous up-counter
- D: Synchronous down-counter
View Answer
A
Q192: The sequence of states that are implemented by a n-bit Johnson counter is
- A: n+2 (n plus 2)
- B: 2n (n multiplied by 2)
- C: 2^n (2 raise to power n)
- D: n^2 (n raise to power 2)
View Answer
B
Q193: "A + B = B + A" is __________
- A: Demorgan‟s Law
- B: Distributive Law
- C: Commutative Law
- D: Associative Law
View Answer
C
Q194: An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is _______
- A: Using a single comparator
- B: Using Iterative Circuit based Comparators
- C: Connecting comparators in vertical hierarchy
- D: Extra logic gates are always required
View Answer
B
Q195: Demultiplexer is also called
- A: Data selector
- B: Data router
- C: Data distributor
- D: Data encoder
View Answer
C
Q196: A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is
- A: 10 mW
- B: 25 mW
- C: 64 mW
- D: 1024
View Answer
B
Q197: ____________ counters as the name indicates are not triggered simultaneously.
- A: Asynchronous
- B: Synchronous
- C: Positive-Edge triggered
- D: Negative-Edge triggered
View Answer
A
Q198: A synchronous decade counter will have _______ flip-flops
- A: 3
- B: 4
- C: 7
- D: 10
View Answer
B
Q199: ________ is used to minimize the possible no. of states of a circuit.
- A: State assignment
- B: State reduction
- C: Next state table
- D: State diagram
View Answer
A
Q200: The alternate solution for a demultiplexer-register combination circuit is _________
- A: Parallel in / Serial out shift register
- B: Serial in / Parallel out shift register
- C: Parallel in / Parallel out shift register
- D: Serial in / Serial Out shift register
View Answer
B