Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Multiple Choice Questions
Q351: The structural RTL for shift instructions uses what type of hardware to manage multiple-bit shifts?
- A: Multiplexer
- B: ALSU
- C: Barrel shifter
- D: Cache memory
View Answer
C
Q352: What is the width of the FALCON-A processor bus?
- A: 8-bits
- B: 16-bits
- C: 32-bits
- D: 64-bits
View Answer
B
Q353: How many registers does the FALCON-A have compared to the SRC?
- A: FALCON-A has 8 registers, SRC has 32 registers.
- B: FALCON-A has 16 registers, SRC has 64 registers.
- C: FALCON-A has 32 registers, SRC has 8 registers.
- D: FALCON-A and SRC have the same number of registers.
View Answer
A
Q354: In FALCON-A, what is the purpose of registers A and AH?
- A: They store 8-bit operands.
- B: They store 16-bit operands.
- C: They store the 32-bit result of multiplication/division operations.
- D: They store addresses only.
View Answer
C
Q355: What does the mul instruction output in FALCON-A?
- A: A 16-bit result
- B: A 32-bit result with the higher 16-bits in register CH
- C: A 64-bit result
- D: A result stored entirely in register C
View Answer
B
Q356: What happens during step T5 in the structural RTL for the shr instruction?
- A: Data is shifted left.
- B: The contents of register ra are shifted right by one bit.
- C: The contents of register rb are shifted right by N bits.
- D: The contents of register rc are incremented.
View Answer
C
Q357: What does the div instruction in FALCON-A do in step T6?
- A: It stores the remainder in register C.
- B: It moves the quotient to register ra.
- C: It transfers the remainder to the default register R[0].
- D: It performs the multiplication of two registers.
View Answer
C
Q358: In the addi ra, rb, c1 instruction, what is the value of c1?
- A: A constant value stored in the program counter
- B: A constant value stored in the instruction
- C: A 32-bit immediate value
- D: A signed 5-bit immediate value
View Answer
D
Q359: How is sign extension performed for a 5-bit constant c1?
- A: By copying the sign bit to the leftmost 11 positions.
- B: By copying the constant to the rightmost 5 positions.
- C: By copying the sign bit to the rightmost 8 positions.
- D: By appending zeros to the rightmost position.
View Answer
A
Q360: Which instruction tests whether the contents of register ra are zero before jumping to a new address?
- A: jnz
- B: jpl
- C: jz
- D: jmi
View Answer
C