Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Multiple Choice Questions
Q331: The Program Counter (PC) holds ______.
- A: The memory address to be accessed
- B: Address of next instruction
- C: Register operation
- D: Control signals
View Answer
B
Q332: Register A and C in the data path are used for ______.
- A: Holding control signals
- B: Temporary storage of operands
- C: Controlling bus timing
- D: Register renaming
View Answer
B
Q333: What does the ALSU (Arithmetic Logic Shift Unit) do in the data path?
- A: Transfers data to memory
- B: Performs arithmetic/logic operations
- C: Shifts data between registers
- D: Generates control signals
View Answer
B
Q334: In processor design, what is the primary purpose of the Timing Step Generator?
- A: To synchronize control signals
- B: To increment the Program Counter
- C: To ensure correct timing of operations
- D: To generate control unit signals
View Answer
C
Q335: How many general-purpose registers are in the SRC's register file?
- A: 16
- B: 64
- C: 32
- D: 128
View Answer
C
Q336: What does the Structural RTL description represent in processor design?
- A: Instruction fetch phase
- B: Abstract operations of CPU
- C: Actual hardware implementation
- D: Instruction scheduling
View Answer
C
Q337: Which component generates the control signals required for executing RTL instructions?
- A: ALU
- B: Control Unit
- C: Program Counter
- D: Timing step generator
View Answer
B
Q338: The structural RTL for instruction fetch takes how many time steps?
- A: 2
- B: 3
- C: 4
- D: 5
View Answer
B
Q339: The sub instruction 'sub ra, rb, rc' takes how many timing steps in execution?
- A: 2
- B: 4
- C: 3
- D: 6
View Answer
C
Q340: In the add instruction 'add ra, rb, rc', what is the final time step where the result is stored?
- A: T3
- B: T4
- C: T5
- D: T6
View Answer
C