System Programming MCQs with Answers
Practice important System Programming MCQs with answers and explanations.
Chapter: 134
Q2861:
Data movement within a core's registers typically costs ________.
A. Tens of cycles
B. Zero cycles
C. Less than one cycle
D. Hundreds of cycles
Correct Answer:
C
Chapter: 134
Q2862:
Data transfer between cores through main memory is ________ than within a core.
A. Slower
B. Faster
C. Same speed
D. Irrelevant
Correct Answer:
A
Chapter: 134
Q2863:
Memory barriers help maintain ________ across multiple processor cores.
A. Instruction cycles
B. Cache coherency
C. Thread count
D. Disk usage
Correct Answer:
B
Chapter: 134
Q2864:
Cache coherency is not fully ensured by using ________ alone.
A. L1 cache
B. Shared memory
C. Volatile qualifier
D. Heap memory
Correct Answer:
C
Chapter: 134
Q2865:
Each core in a dual-core chip architecture usually has ________ cache for instructions and data.
A. Shared
B. Level-2
C. Individual Level-1
D. Dynamic
Correct Answer:
C
Chapter: 134
Q2866:
Which memory level is common among all cores on the same chip?
A. L0
B. L1
C. L2
D. L3
Correct Answer:
C
Chapter: 134
Q2867:
Memory barriers are necessary for ________ systems.
A. Single-threaded
B. Multi-core
C. Static
D. Batch
Correct Answer:
B
Chapter: 134
Q2868:
Processor cores might see values in a different order without using ________.
A. Stack memory
B. Volatile
C. Memory barriers
D. Mutexes
Correct Answer:
C
Chapter: 134
Q2869:
Updating a variable in core 0 does not ensure immediate visibility in core 3 without ________.
A. Shared pointers
B. Paging
C. Memory fence
D. Virtualization
Correct Answer:
C
Chapter: 134
Q2870:
Interlocked functions are used to implement ________.
A. Memory barriers
B. Deadlock prevention
C. Paging mechanisms
D. Registers
Correct Answer:
A
Chapter: 134
Q2871:
Cache coherency ensures all cores have ________ view of shared variables.
A. Random
B. Local
C. Consistent
D. Exclusive
Correct Answer:
C
Chapter: 134
Q2872:
Memory barriers can impact performance due to ________ overhead.
A. Synchronization
B. Network
C. Heap
D. GPU
Correct Answer:
A
Chapter: 134
Q2873:
Moving data from one core to another via main memory may take ________ cycles.
A. Less than one
B. A few
C. Hundreds of
D. Two
Correct Answer:
C
Chapter: 134
Q2874:
Which of the following ensures cache is coherent across all processors?
A. Register allocation
B. Static linking
C. Memory barriers
D. File buffers
Correct Answer:
C
Chapter: 134
Q2875:
Using only volatile in a multi-core system might lead to ________ values across threads.
A. Synchronized
B. Incoherent
C. Stable
D. Protected
Correct Answer:
B
Chapter: 134
Q2876:
Memory barrier ensures updated values are written to ________.
A. Temporary stack
B. Main memory
C. Network buffer
D. Index buffer
Correct Answer:
B
Chapter: 134
Q2877:
The diagram of dual-core chips shows each core with its own ________.
A. Instruction pointer
B. Hard disk
C. L1 cache
D. GPU unit
Correct Answer:
C
Chapter: 135
Q2878:
Interlocked functions are best suited for operations like ________.
A. file handling
B. incrementing, decrementing, and exchanging
C. memory allocation
D. conditional branching
Correct Answer:
B
Chapter: 135
Q2879:
Which of the following is a basic interlocked function?
A. InterlockedFlush()
B. InterlockedCopy()
C. InterlockedIncrement()
D. InterlockedLock()
Correct Answer:
C
Chapter: 135
Q2880:
Interlocked functions generate a ________.
A. memory leak
B. memory barrier
C. garbage value
D. process fork
Correct Answer:
B