Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Chapter: 13
Q361:
In the Adjacent 1s Detector circuit, what is the number of minterms that are used in the POS expression?
A. 8
B. 4
C. 10
D. 12
Correct Answer:
A
Chapter: 13
Q362:
Which of the following circuits can have either active-high or active-low inputs?
A. Only AND gates
B. Only OR gates
C. Combinational logic circuits
D. Only NOT gates
Correct Answer:
C
Chapter: 14
Q363:
What does the output P in an odd-parity generator circuit represent?
A. The number of 1s in the 4-bit input
B. The state of the parity bit
C. The sum of input bits
D. The carry bit of the input
Correct Answer:
B
Chapter: 14
Q364:
How many possible combinations are there for a 4-bit input in an odd-parity generator?
A. 8
B. 16
C. 256
D. 64
Correct Answer:
B
Chapter: 14
Q365:
What is the Boolean expression for the odd-parity generator circuit?
A. (C ⊕ D) ⊕ (A ⊕ B)
B. (A ⊕ B) ⊕ (C ⊕ D)
C. (A ⊕ B) + (C ⊕ D)
D. (A ⊕ B) · (C ⊕ D)
Correct Answer:
B
Chapter: 14
Q366:
Which gate is used to detect parity errors in the receiver circuit?
A. XNOR gate
B. XOR gate
C. AND gate
D. OR gate
Correct Answer:
B
Chapter: 14
Q367:
What is the output of the XOR gate for inputs A=1 and B=0?
A. zero
B. 1
C. 1
Correct Answer:
B
Chapter: 14
Q368:
What is the output of the XNOR gate for inputs A=1 and B=0?
A. 1
B. zero
C. 1
Correct Answer:
B
Chapter: 14
Q369:
In the function table for a Half-Adder, what is the output for A=1, B=1?
A. Sum=0, Carry Out=0
B. Sum=1, Carry Out=0
C. Sum=0, Carry Out=1
D. Sum=1, Carry Out=1
Correct Answer:
D
Chapter: 14
Q370:
How is a Full-Adder implemented using Half-Adder circuits?
A. By combining two Half-Adders
B. By using a single XOR gate
C. By using a single AND gate
D. By connecting a Half-Adder with a NOT gate
Correct Answer:
A
Chapter: 14
Q371:
What is the Boolean expression for the Sum output of a Full-Adder?
A. A ⊕ B ⊕ C
B. (A ⊕ B) + C
C. (A · B) ⊕ C
D. A ⊕ (B ⊕ C)
Correct Answer:
A
Chapter: 14
Q372:
Which ICs are used for 4-bit parallel adders with Look-Ahead Carry Circuitry?
A. 74LS83A and 74LS283
B. 74LS00 and 74LS04
C. 74LS08 and 74LS32
D. 74LS02 and 74LS20
Correct Answer:
A
Chapter: 14
Q373:
What is the purpose of Look-Ahead Carry Circuits?
A. To delay carry propagation
B. To speed up carry propagation
C. To eliminate carry propagation
D. To detect carry errors
Correct Answer:
B
Chapter: 14
Q374:
In a 4-bit Parallel Adder, what is the delay caused by carry propagation through the full adders?
A. 30 nsec
B. 60 nsec
C. 90 nsec
D. 120 nsec
Correct Answer:
D
Chapter: 14
Q375:
How are Look-Ahead Carry Generator circuits designed to speed up calculations?
A. By using additional XOR gates
B. By using additional AND gates
C. By using additional OR gates
D. By evaluating carry generation in parallel
Correct Answer:
B
Chapter: 14
Q376:
What is the delay for the carry output C4 in a 4-bit Look-Ahead Carry Generator circuit?
A. After 1 gate delay
B. After 2 gate delays
C. After 3 gate delays
D. After 4 gate delays
Correct Answer:
B
Chapter: 15
Q377:
What does BCD stand for in digital systems?
A. Binary Coded Decimal
B. Binary Code Decimal
C. Binary Complete Decimal
D. Binary Count Decimal
Correct Answer:
A
Chapter: 15
Q378:
How many 4-bit combinations are considered valid in BCD?
A. 6
B. 10
C. 16
D. 8
Correct Answer:
B
Chapter: 15
Q379:
What is the purpose of adding a 6 to the result in BCD Addition?
A. To correct an overflow error
B. To convert an invalid BCD number to a valid one
C. To decrease the sum by 6
D. To increase the digit by 6
Correct Answer:
B
Chapter: 15
Q380:
What circuit checks if the output of the first Adder has exceeded 9 in BCD Addition?
A. Invalid BCD Number Detector
B. Carry Look-Ahead Circuit
C. Parity Checker
D. Overflow Detector
Correct Answer:
A