Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 41
Q901:
What is the average access time if the hit time is 12 ns and the miss time is 100 ns?
A. 29.6 ns
B. 20 ns
C. 25 ns
D. 15 ns
Correct Answer:
A
Chapter: 41
Q902:
What is the access time for requests that reach the cache in Example 5?
A. 100 ns
B. 5 ns
C. 80,099 ns
D. 8 ms
Correct Answer:
C
Chapter: 41
Q903:
In a fully associative cache with a write miss, which option allocates the block?
A. Write-Through
B. Write Allocate
C. No-Write Allocate
D. Write-Back
Correct Answer:
B
Chapter: 41
Q904:
If a memory system has a latency of 25ns and transfers 2 bytes of data per access, what is its bandwidth?
A. 6.66 x 10^7 bytes/s
B. 3.33 x 10^7 bytes/s
C. 5.66 x 10^7 bytes/s
D. 7.66 x 10^7 bytes/s
Correct Answer:
A
Chapter: 41
Q905:
What is the miss penalty for the processor in Example 12?
A. 30 clock cycles
B. 20 clock cycles
C. 10 clock cycles
D. 15 clock cycles
Correct Answer:
A
Chapter: 41
Q906:
What happens when a write miss occurs with a No-Write Allocate policy?
A. Block is allocated
B. Only memory is modified
C. No action
D. Cache is flushed
Correct Answer:
B
Chapter: 41
Q907:
How many cycles are required to fetch a block from main memory if it takes 20 cycles to transfer 2 bytes of data for a 128-byte cache line?
A. 1280 cycles
B. 640 cycles
C. 320 cycles
D. 2560 cycles
Correct Answer:
A
Chapter: 41
Q908:
In a 64KB direct-mapped cache, how many bits are required to select the cache line?
A. 5 bits
B. 10 bits
C. 11 bits
D. 12 bits
Correct Answer:
C
Chapter: 41
Q909:
How many sets are there in a 2-way set-associative cache with 64KB capacity and 16-byte lines?
A. 1024
B. 2048
C. 4096
D. 512
Correct Answer:
B
Chapter: 41
Q910:
If a cache with 64KB capacity and 16-byte lines contains 4096 lines, what is the number of bits required to select the set?
A. 10 bits
B. 11 bits
C. 12 bits
D. 13 bits
Correct Answer:
B
Chapter: 41
Q911:
What is the performance ratio when there are no cache misses?
A. 1.72 times faster
B. 2.5 times faster
C. 1.0 times faster
D. 3.0 times faster
Correct Answer:
A
Chapter: 42
Q912:
What is the main focus of the chapter on I/O subsystems?
A. Memory management
B. Data storage
C. Performance measurement
D. Software optimization
Correct Answer:
C
Chapter: 42
Q913:
In a producer-server model, what affects latency and response time?
A. Number of tasks in queue
B. Task completion speed
C. All of the above
D. None of the above
Correct Answer:
C
Chapter: 42
Q914:
Which of the following methods is NOT used to measure I/O subsystem performance?
A. Simulation
B. Queuing Theory
C. Linear regression
D. Execution time
Correct Answer:
C
Chapter: 42
Q915:
The loss system does not have any provision for what?
A. Tasks
B. Buffer
C. Controllers
D. CPUs
Correct Answer:
B
Chapter: 42
Q916:
In a delay system, what can happen if the call party is busy?
A. Call disconnects
B. Call waiting
C. Immediate disconnection
D. Busy signal
Correct Answer:
B
Chapter: 42
Q917:
What does Little's Law relate to in I/O systems?
A. Arrival rate and response time
B. Latency and throughput
C. Queue length and service time
Correct Answer:
A
Chapter: 42
Q918:
Server utilization must be between which values?
A. 0 and 1
B. 0 and 100
C. 1 and 10
D. 0 and infinity
Correct Answer:
A
Chapter: 42
Q919:
In the example given, if the server utilization is 0.5, what is the mean number of I/O requests in the queue?
A. 0.5
B. 1
C. 2
D. 0.25
Correct Answer:
A
Chapter: 42
Q920:
What does the Poisson distribution help characterize?
A. Linear events
B. Random events
C. Static events
D. Continuous events
Correct Answer:
B