Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Chapter: 6
Q181:
What is the purpose of the enable line in an n-bit register?
A. To control input clock
B. To store a binary number
C. To select output
D. To store a single bit
Correct Answer:
B
Chapter: 6
Q182:
How many connections are required for 5 m-bit registers in a point-to-point scheme?
A. 5
B. 15
C. 20
D. 25
Correct Answer:
C
Chapter: 6
Q183:
What is the main solution to avoid excessive connections in register interconnections?
A. Using a bus architecture
B. Using more wires
C. Using more registers
D. Using fewer registers
Correct Answer:
A
Chapter: 6
Q184:
What does a bus provide in a computer system?
A. Memory storage
B. A shared data path
C. Instruction processing
D. Logical operations
Correct Answer:
B
Chapter: 6
Q185:
Which of the following can be used as control signals for bus communication?
A. Open collector gates
B. Multiplexers
C. Tri-state buffers
D. All of the above
Correct Answer:
D
Chapter: 6
Q186:
How many registers are connected using a bus in the given example?
A. 2
B. 4
C. 6
D. 8
Correct Answer:
D
Chapter: 6
Q187:
What type of buffer is used to enable a register to transfer data onto the bus?
A. Dual-state buffer
B. Bi-state buffer
C. Tri-state buffer
D. Multi-state buffer
Correct Answer:
C
Chapter: 6
Q188:
In the example R4← R3 + R2, which component performs the addition?
A. A multiplexer
B. A 4-bit adder
C. A tri-state buffer
D. A bus
Correct Answer:
B
Chapter: 6
Q189:
What does the control signal Cout do during the register transfer?
A. Loads the bus
B. Loads the register
C. Writes the bus contents to the register
D. Enables the adder
Correct Answer:
C
Chapter: 6
Q190:
How many clock periods does a 9-bit shift take in a traditional shift register?
A. 2
B. 9
C. 6
D. 3
Correct Answer:
B
Chapter: 6
Q191:
What is used to reduce shift delays in a register?
A. Multiplexer
B. Barrel shifter
C. Counter
D. Adder
Correct Answer:
B
Chapter: 6
Q192:
In a barrel shifter, how many shifts are performed with the control signal 11 on (S1, S0)?
A. 1
B. 2
C. 3
D. 4
Correct Answer:
C
Chapter: 6
Q193:
To perform the operation R4← ror R3 (2 times), which control line settings are used on the barrel shifter?
A. nb0=1, nb1=0
B. nb0=0, nb1=1
C. nb0=1, nb1=1
D. nb0=0, nb1=0
Correct Answer:
B
Chapter: 6
Q194:
Which of the following allows a register to shift data during a single clock period?
A. Shift register
B. Counter
C. Barrel shifter
D. Multiplexer
Correct Answer:
C
Chapter: 6
Q195:
What is the purpose of the register C in the R4← R3 + R2 operation?
A. Store the final result
B. Hold one operand
C. Control the bus
D. Activate the adder
Correct Answer:
B
Chapter: 6
Q196:
What type of shift operation is performed when the control inputs nb1=1, nb0=0?
A. Left shift
B. Right shift
C. Rotate
D. No shift
Correct Answer:
B
Chapter: 6
Q197:
In the example of the shift operation, where is the shifted result stored after using the barrel shifter?
A. Register R3
B. Register C
C. Register R4
D. The bus
Correct Answer:
C
Chapter: 7
Q198:
What does FALCON-A stand for?
A. First Architecture for Learning Computer Organization and Networks
B. First Architecture for Learning Computer Programming
C. First Architecture for Learning Computer Networks
D. None of the above
Correct Answer:
A
Chapter: 7
Q199:
Which components define any instruction set architecture?
A. Operations, Data Access Mode, Representation of Operations
B. Operations, Memory Size, Processor Speed
C. Data Type, Instruction Length, Memory Size
D. Operations, Data Type, Control Logic
Correct Answer:
A
Chapter: 7
Q200:
Which of the following is NOT a category of instructions that processors need to support?
A. Arithmetic
B. Logic
C. Control
D. Sorting
Correct Answer:
D