Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Multiple Choice Questions
Q501: What device is used to implement a Quad 1-of-4 MUX according to the document?
- A: GAL16V8
- B: GAL20V8
- C: GAL22V10
- D: GAL10V8
View Answer
B
Q502: In the given implementation, which input pins are used for select lines in the Quad 1-of-4 MUX?
- A: A0, A1
- B: S0, S1
- C: D0, D1
- D: B0, B1
View Answer
B
Q503: What is the output of the Quad 1-of-4 MUX when S1 = 0, S0 = 1, A0 = 1, A1 = 0, A2 = 0, A3 = 0?
- A: 1
- B: zero
- C: 1, 0, 0, 0
- D: 0, 1, 0, 0
View Answer
A
Q504: What is the output of the Quad 1-of-4 MUX when S1 = 1, S0 = 0, B0 = 1, B1 = 0, B2 = 0, B3 = 0?
- A: 1
- B: zero
- C: 1, 0, 0, 0
- D: 0, 1, 0, 0
View Answer
A
Q505: Which logic gates are used in an S-R NAND latch?
- A: NOR gates
- B: NAND gates
- C: AND gates
- D: OR gates
View Answer
B
Q506: What happens when both inputs S and R are 0 in an S-R NAND latch?
- A: Both outputs are set to 0
- B: Both outputs are set to 1
- C: One output is 1 and the other is 0
- D: Both outputs are invalid
View Answer
B
Q507: What is the output when S=0 and R=1 for an S-R NAND latch?
- A: Q = 1, Q = 0
- B: Q = 0, Q = 1
- C: Both outputs are invalid
- D: Q = 1, Q = 1
View Answer
A
Q508: In an S-R NOR latch, what is the output when S=1 and R=0?
- A: Q = 0, Q = 1
- B: Q = 1, Q = 0
- C: Both outputs are 1
- D: Both outputs are 0
View Answer
B
Q509: What does the NOR gate based S-R latch do with inputs S=0 and R=1?
- A: Sets Q to 1 and Q to 0
- B: Sets Q to 0 and Q to 1
- C: Maintains previous state
- D: Invalid state
View Answer
A
Q510: What is a key difference between NAND and NOR based S-R latches?
- A: NAND has active-high inputs, NOR has active-low inputs
- B: NAND has active-low inputs, NOR has active-high inputs
- C: NAND and NOR latches are identical
- D: Both use the same input logic
View Answer
B