Digital Logic and Design MCQs with Answers
Practice important Digital Logic and Design MCQs with answers and explanations.
Multiple Choice Questions
Q361: In the Adjacent 1s Detector circuit, what is the number of minterms that are used in the POS expression?
- A: 8
- B: 4
- C: 10
- D: 12
View Answer
A
Q362: Which of the following circuits can have either active-high or active-low inputs?
- A: Only AND gates
- B: Only OR gates
- C: Combinational logic circuits
- D: Only NOT gates
View Answer
C
Q363: What does the output P in an odd-parity generator circuit represent?
- A: The number of 1s in the 4-bit input
- B: The state of the parity bit
- C: The sum of input bits
- D: The carry bit of the input
View Answer
B
Q364: How many possible combinations are there for a 4-bit input in an odd-parity generator?
- A: 8
- B: 16
- C: 256
- D: 64
View Answer
B
Q365: What is the Boolean expression for the odd-parity generator circuit?
- A: (C ⊕ D) ⊕ (A ⊕ B)
- B: (A ⊕ B) ⊕ (C ⊕ D)
- C: (A ⊕ B) + (C ⊕ D)
- D: (A ⊕ B) · (C ⊕ D)
View Answer
B
Q366: Which gate is used to detect parity errors in the receiver circuit?
- A: XNOR gate
- B: XOR gate
- C: AND gate
- D: OR gate
View Answer
B
Q367: What is the output of the XOR gate for inputs A=1 and B=0?
- A: zero
- B: 1
- C: 1
- D: 0
View Answer
B
Q368: What is the output of the XNOR gate for inputs A=1 and B=0?
- A: 1
- B: zero
- C: 1
- D: 0
View Answer
B
Q369: In the function table for a Half-Adder, what is the output for A=1, B=1?
- A: Sum=0, Carry Out=0
- B: Sum=1, Carry Out=0
- C: Sum=0, Carry Out=1
- D: Sum=1, Carry Out=1
View Answer
D
Q370: How is a Full-Adder implemented using Half-Adder circuits?
- A: By combining two Half-Adders
- B: By using a single XOR gate
- C: By using a single AND gate
- D: By connecting a Half-Adder with a NOT gate
View Answer
A