Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Multiple Choice Questions
Q901: What is the average access time if the hit time is 12 ns and the miss time is 100 ns?
- A: 29.6 ns
- B: 20 ns
- C: 25 ns
- D: 15 ns
View Answer
A
Q902: What is the access time for requests that reach the cache in Example 5?
- A: 100 ns
- B: 5 ns
- C: 80,099 ns
- D: 8 ms
View Answer
C
Q903: In a fully associative cache with a write miss, which option allocates the block?
- A: Write-Through
- B: Write Allocate
- C: No-Write Allocate
- D: Write-Back
View Answer
B
Q904: If a memory system has a latency of 25ns and transfers 2 bytes of data per access, what is its bandwidth?
- A: 6.66 x 10^7 bytes/s
- B: 3.33 x 10^7 bytes/s
- C: 5.66 x 10^7 bytes/s
- D: 7.66 x 10^7 bytes/s
View Answer
A
Q905: What is the miss penalty for the processor in Example 12?
- A: 30 clock cycles
- B: 20 clock cycles
- C: 10 clock cycles
- D: 15 clock cycles
View Answer
A
Q906: What happens when a write miss occurs with a No-Write Allocate policy?
- A: Block is allocated
- B: Only memory is modified
- C: No action
- D: Cache is flushed
View Answer
B
Q907: How many cycles are required to fetch a block from main memory if it takes 20 cycles to transfer 2 bytes of data for a 128-byte cache line?
- A: 1280 cycles
- B: 640 cycles
- C: 320 cycles
- D: 2560 cycles
View Answer
A
Q908: In a 64KB direct-mapped cache, how many bits are required to select the cache line?
- A: 5 bits
- B: 10 bits
- C: 11 bits
- D: 12 bits
View Answer
C
Q909: How many sets are there in a 2-way set-associative cache with 64KB capacity and 16-byte lines?
- A: 1024
- B: 2048
- C: 4096
- D: 512
View Answer
B
Q910: If a cache with 64KB capacity and 16-byte lines contains 4096 lines, what is the number of bits required to select the set?
- A: 10 bits
- B: 11 bits
- C: 12 bits
- D: 13 bits
View Answer
B