Advanced Computer Architecture MCQs with Answers
Practice important Advanced Computer Architecture MCQs with answers and explanations.
Multiple Choice Questions
Q711: How many cycles per second are spent handling I/O when using interrupts only?
- A: 2400000
- B: 3395000
- C: 200000
- D: 1000000
View Answer
A
Q712: What is the typical overhead incurred by a DMA operation?
- A: 2000 cycles
- B: 1000 cycles
- C: 500 cycles
- D: 5000 cycles
View Answer
A
Q713: To achieve a high data transfer rate, the CPU must ___________.
- A: Stay idle
- B: Continuously poll
- C: Use DMA
- D: Increase interrupts
View Answer
C
Q714: What is the main advantage of Direct Memory Access (DMA)?
- A: Higher transfer rates
- B: Lower cost
- C: Increased CPU workload
- D: Reduced memory usage
View Answer
A
Q715: In DMA, which component is typically the master during a bus cycle?
- A: Peripheral Device
- B: CPU
- C: DMA Controller
- D: Memory
View Answer
B
Q716: What does the term "cycle stealing" refer to in DMA?
- A: The CPU taking control of the bus
- B: The DMA module taking control of the bus
- C: The CPU sending data
- D: The DMA module ignoring requests
View Answer
B
Q717: Which of the following is NOT a DMA transfer combination?
- A: Memory to memory
- B: Memory to peripheral
- C: Peripheral to peripheral
- D: CPU to peripheral
View Answer
D
Q718: In the DMA transfer protocol, what signal does the DMA controller send to the CPU at the end of a transfer?
- A: Reset signal
- B: Release signal
- C: Bus Grant signal
- D: Interrupt signal
View Answer
D
Q719: Which step involves the DMA controller transferring the entire block of data?
- A: 1st Step
- B: 2nd Step
- C: 3rd Step
- D: Setup Step
View Answer
B
Q720: What is the main disadvantage of using DMA?
- A: Low transfer rates
- B: Complexity and cost
- C: Slower data transfer
- D: CPU overload
View Answer
B