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Advanced Computer Architecture MCQs with Answers

Practice important Advanced Computer Architecture MCQs with answers and explanations.

Multiple Choice Questions

Q391: In the instruction fetch phase, what control signal enables the memory read operation?
  • A: LMBR
  • B: MRead
  • C: LC
  • D: LPC
View Answer
B

Q392: The LPC control signal in SRC allows the Program Counter to be:
  • A: Loaded with the incremented value
  • B: Written into the Memory Address Register
  • C: Read from the internal data bus
  • D: Written onto external CPU bus
View Answer
A

Q393: Which of the following signals is activated to enable the tri-state buffers of the Memory Buffer Register (MBR)?
  • A: MARout
  • B: PCout
  • C: MBRout
  • D: LIR
View Answer
C

Q394: The LIR control signal in SRC is used to:
  • A: Enable tri-state buffers
  • B: Load the Instruction Register
  • C: Load the Memory Buffer Register
  • D: Enable Program Counter
View Answer
B

Q395: Which control signal writes the contents of register C onto the internal processor bus?
  • A: LC
  • B: Cout
  • C: PCout
  • D: MARout
View Answer
B

Q396: What does the RAE control signal enable in the register selection process?
  • A: Enables reading from register A
  • B: Enables writing to register A
  • C: Selects the register based on instruction
  • D: Enables data transfer to Memory Buffer
View Answer
C

Q397: The MBR holds values read from:
  • A: ALU
  • B: Memory
  • C: Program Counter
  • D: Instruction Register
View Answer
B

Q398: The control signal R2BUS enables which of the following?
  • A: Writing register contents onto internal bus
  • B: Writing ALU results to register
  • C: Reading memory contents to bus
  • D: Writing PC onto external data bus
View Answer
A

Q399: The ALSU is responsible for which operation in the SRC data path?
  • A: Control signal generation
  • B: Address translation
  • C: Arithmetic and logical operations
  • D: Bus management
View Answer
C

Q400: The memory buffer register (MBR) is connected to which of the following?
  • A: External CPU data bus
  • B: Program Counter
  • C: Instruction Register
  • D: Arithmetic Unit
View Answer
A

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